The present invention relates to integrated circuits including graphics processors generally, and more particularly to the efficient utilization of storage buffers in graphics processors.
Graphics processors form images for display on computer monitors by processing primitives. These primitives each form a portion of the image and are typically points, lines, and triangles. Each of these primitives are defined by their endpoints, which are referred to as vertices.
Each vertex is defined by data including its position, color, and other attributes. In advanced processors, this data is very large, and can be over a hundred or hundreds of bits in size. Accordingly, storing these vertices requires a large amount of circuitry. This circuitry consumes die area, thus increasing circuit cost and layout complexity, and also increasing circuit power dissipation.
These vertices undergo several stages of processing during the generation of an image for display. As such, they are stored at various times during this processing. Each time these vertices are stored, these large storage circuits are required. If more efficient use of the storage circuits could be made, the number of storage circuits could be reduced.
Thus, what is needed are circuits, methods, and apparatus that utilize these storage buffers more efficiently, thereby reducing the number of storage buffers that need to be included on a graphics processor integrated circuit. This reduction reduces circuit cost and die area, simplifies its layout, and reduces its power dissipation.